Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 {\mu}m$^2$ for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.Comment: Supplementary information include

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 {\mu}m$^2$ for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.Comment: Supplementary information include

Fast characterization of input-output behavior of non-charge-based logic devices by machine learning

Non-charge-based logic devices are promising candidates for the replacement of conventional complementary metal-oxide semiconductors (CMOS) devices. These devices utilize magnetic properties to store or process information making them power efficient. Traditionally, to fully characterize the input-output behavior of these devices a large number of micromagnetic simulations are required, which makes the process computationally expensive. Machine learning techniques have been shown to dramatically decrease the computational requirements of many complex problems. We use state-of-the-art data-efficient machine learning techniques to expedite the characterization of their behavior. Several intelligent sampling strategies are combined with machine learning (binary and multi-class) classification models. These techniques are applied to a magnetic logic device that utilizes direct exchange interaction between two distinct regions containing a bistable canted magnetization configuration. Three classifiers were developed with various adaptive sampling techniques in order to capture the input-output behavior of this device. By adopting an adaptive sampling strategy, it is shown that prediction accuracy can approach that of full grid sampling while using only a small training set of micromagnetic simulations. Comparing model predictions to a grid-based approach on two separate cases, the best performing machine learning model accurately predicts 99.92% of the dense test grid while utilizing only 2.36% of the training data respectively

Material-Device-Circuit Co-Design of 2-D Materials-Based Lateral Tunnel FETs

In this paper, the 2-D materials-based lateral TFETs are holistically assessed by co-optimizing the material parameters, device designs, and digital circuit figure-of-merits, e.g., energy consumption and delay. Effect of material parameters such as effective mass and bandgap are studied using a two-band quantum simulation approach in the ballistic regime. The selection of 2-D material parameters is discussed from the energy-delay perspective. Single-gate and double-gate 2-D TFETs are compared with the optimum material parameters. Using a simple analytical model for 2-D TFETs, the quantum simulation results for different materials and device designs are analyzed. We show that the gate-to-source fringing fields play a significant role in 2-D TFETs performance. To mitigate the effect of fringing fields on tunneling lengths, an interfacial layer (IL) is introduced between high- $\kappa$ and 2-D material, resulting a 3– $4\times$ increase in ON current. Using circuit-level metrics, we show that a tri-layer black phosphorus (BP) TFET using IL can outperform monolayer BP MOSFETs for the supply voltages below 0.5 V

Energy filtering in silicon nanowires and nanosheets using a geometric superlattice and its use for steep-slope transistors

This paper investigates energy filtering in silicon nanowires and nanosheets by resonant electron tunneling through a geometric superlattice. A geometric superlattice is any kind of periodic geometric feature along the transport direction of the nanowire or nanosheet. Multivalley quantum-transport simulations are used to demonstrate the manifestation of minibands and minibandgaps in the transmission spectra of such a superlattice. We find that the presence of different valleys in the conduction band of silicon favors a nanowire with a rectangular cross section for effective energy filtering. The obtained energy filter can consequently be used in the source extension of a field-effect transistor to prevent high-energy electrons from contributing to the leakage current. Self-consistent Schrodinger-Poisson simulations in the ballistic limit show minimum subthreshold swings of 6 mV/decade for geometric superlattices with indentations. The obtained theoretical performance metrics for the simulated devices are compared with conventional III-V superlatticeFETs and TunnelFETs. The adaptation of the quantum transmitting boundary method to the finite-element simulation of 3-D structures with anisotropic effective mass is presented in Appendixes A and B. Our results bare relevance in the search for steep-slope transistor alternatives which are compatible with the silicon industry and can overcome the power-consumption bottleneck inherent to standard CMOS technologies. Published by AIP Publishing

Modeling and Tackling Resistivity Scaling in Metal Nanowires

A self-consistent analytical solution of the multi-subband Boltzmann transport equation with collision term describing grain boundary and surface roughness scattering is presented to study the resistivity scaling in metal nanowires. The different scattering mechanisms and the influence of their statistical parameters are analyzed. Instead of a simple power law relating the height or width of a nanowire to its resistivity, the picture appears to be more complicated due to quantum-mechanical scattering and quantization effects, especially for surface roughness scattering.status: publishe

Resistivity scaling and electron relaxation times in metallic nanowires

We study the resistivity scaling in nanometer-sized metallic wires due to surface roughness and grain-boundaries, currently the main cause of electron scattering in nanoscaled interconnects. The resistivity has been obtained with the Boltzmann transport equation, adopting the relaxation time approximation of the distribution function and the effective mass approximation for the conducting electrons. The relaxation times are calculated exactly, using Fermi's golden rule, resulting in a correct relaxation time for every sub-band state contributing to the transport. In general, the relaxation time strongly depends on the sub-band state, something that remained unclear with the methods of previous work. The resistivity scaling is obtained for different roughness and grain-boundary properties, showing large differences in scaling behavior and relaxation times. Our model clearly indicates that the resistivity is dominated by grain-boundary scattering, easily surpassing the surface roughness contribution by a factor of 10.status: publishe

Signature of Ballistic Band-Tail Tunneling Current in Tunnel FET

status: publishe